1. Field of the invention
The present invention relates to an integrated circuit employing NPN power transistors for DC driving an external load, particularly an electric motor, and having a protection against an accidental inversion of polarity of the supply.
2. Description of the prior art
Full-bridge or half-bridge output driving stages, monolithically integrated by employing a junction isolation technique for bidirectional DC driving of motors by means of integrated power switches, are known and widely used. In these integrated power stages the N-type transistors (bipolar NPN or N-channel MOS transistors) are much more efficient than P-type transistors. In practice bridge or half-bridge circuits for high level currents may be economically implemented in an integrated form only if the power switching transistors are of the N-type.
A typical integrated bridge circuit of this kind is shown in FIG. 1. The positive pole of the supply is switched, respectively by the two (high side) NPN power transistors TN1 and TN2, on two output terminals 1 and 2, across which the motor M to be driven is connected. The bridge circuit is completed by two (low side) power transistors TN3 and TN4 which are driven so as to connect to the negative supply pole (ground) the output terminals 1 and 2, respectively. It is also a common practice to drive the two high side switches TN1 and TN2 by means of the two drive PNP transistors TP5 and TP6, respectively, to the base of which the respective drive signals are fed.
The presence of a parasitic diode (respectively D1 and D2 in the circuit diagram of FIG. 1) between an N-type collector C and the P-type substrate S connected to ground of the integrated circuit is intrinsic to such an integrated structure employing a junction-type isolation of an NPN transistor depicted in FIG. 3. In the perspective sectional view of the integrated structure of an NPN transistor of FIG. 3, the presence of this parasitic diode D1 (D2) is schematically shown by means of the relative graphic symbol. The hatched portions of the cross section identify P-type regions while the non-hatched portions identify N-type regions.
Should the supply polarity be accidentally inverted, these parasitic diodes D1 and D2 of the integrated NPN transistors TN1 and TN2 become directly biased and the current passing through these diodes may reach destructive levels.
In order to overcome this problem it is known in the art to use a circuit, such as the one depicted in FIG. 2, wherein a polarity guard diode D3 is employed, which when the supply is accidentally applied with an inverted polarity remains reverse biased thus preventing current flow.
This known solution is not free of drawbacks. In fact, by observing the circuit of FIG. 1, it is easily recognizable that the total voltage drop of the load driving bridge circuit is given by the following expression (for a first diagonal of the bridge): EQU VCE.sub.SAT (TP5)+VBE(TN1)+VCE.sub.SAT (TN4)
or (for the other diagonal of the bridge): EQU VCE.sub.SAT (TP6)+VBE(TN2)+VCE.sub.SAT (TN3)
while in the case of the circuit provided with the guard diode of FIG. 2, the total voltage drop of the circuit is similarly given by the expression (for a first diagonal): EQU V.sub.F (D3)+VCE.sub.SAT (TP5)+VBE(TN1)+VCE.sub.SAT (TN4)
or (for the other diagonal): EQU V.sub.F (D3)+VCE.sub.SAT (TP6)+VBE(TN2)+VCE.sub.SAT (TN3).
It is evident that the use of a diode D3 for protection against polarity inversion of the supply penalizes the electrical efficiency of the circuit by introducing an additional voltage drop V.sub.F (D3) which, in a normal operating condition may be comprised between about 600 mV and 1.2 V.